北京邮电大学学报

  • EI核心期刊

北京邮电大学学报 ›› 2000, Vol. 23 ›› Issue (2): 43-47.

• 研究报告 • 上一篇    下一篇

EPLD可编程器件设计实验开发

黄惠英,费铸增   

  1. 北京邮电大学电子工程系,北京100876
  • 收稿日期:1999-11-18 出版日期:2000-03-10
  • 作者简介:黄惠英(1957-),女,辽宁丹东人,北京邮电大学工程师.

Development of EPLD Programmable Device Design Test

HUANG Hui-ying, FEI Zhu-zeng   

  1. Department of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 1000876,China
  • Received:1999-11-18 Online:2000-03-10

摘要: 应用VLSI技术和CAD技术,根据EPLD可编程技术具有功能集成度高,系统设计加快,设计灵活,可靠性高,费用低的特点,利用美国Altera公司开发的MAX+PLUS软件,研究开发EPLD可编程器件设计专业实验,用于促进学生理论与实际结合及工程实际应用.

关键词: 超大规模集成电路技术, 可擦可编逻辑器件, 超高速集成电路硬件描述语言

Abstract: According to the features of rapid and flexible design, high reliability and low cost of EPLD programmable technology, using VLSI, CAD and MAX+PLUS II developed by Altera company, research and develop EPLD (Erased Programmable Logic Device) design specialty test. This experiment can be used to promote the ability of engineering practice and to combination of practice and theory of students.

Key words: very large scale integration technology , erasable programmable logic device, very high speed integrated circuit hardware description language

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