[1] Shi Weisong, Cao Jie, Zhang Quan, et al. Edge computing:vision and challenges[J]. IEEE Internet of Things Journal, 2016, 3(5):637-646. [2] 王力玉, 陈岚, 郝晓冉, 等. 利用SSD和DRAM构建的扩展内存架构[J]. 西安电子科技大学学报, 2017, 44(3):144-150. Wang Liyu, Chen Lan, Hao Xiaoran, et al. Memory-extended architecture based on the SSD and DRAM[J]. Journal of Xidian University, 2017, 44(3):144-150. [3] 王强, 陈岚, 郝晓冉. 一种基于访存行为地址映射机制的混合内存系统[J]. 小型微型计算机系统, 2014, 35(6):1201-1206. Wang Qiang, Chen Lan, Hao Xiaoran. Hybrid memory system using memory access-aware remapping mechanism[J]. Journal of Chinese Computer Systems, 2014, 35(6):1201-1206. [4] Bock S, Childers B R, Melhem R, et al. Concurrent migration of multiple pages in software-managed hybrid main memory[C]//IEEE International Conference on Computer Design. New York:IEEE Press, 2016:420-423. [5] Ramos L E, Gorbatov E, Bianchini R. Page placement in hybrid memory systems[C]//Proceedings of the 25th International Conference on Supercomputing. New York:ACM Press, 2011:85-95. [6] Jia Gangyong, Han Guangjie, Xie Hongtianchen, et al. Hybrid-LRU caching for optimizing data storage and retrieval in edge computing-based wearable sensors[J]. IEEE Internet of Things Journal, 2019, 6(2):1342-1351. [7] Chen Di, Jin Hai, Liao Xiaofei, et al. MALRU:miss-penalty aware LRU-based cache replacement for hybrid memory systems[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE). New York:IEEE Press, 2017:1086-1091. [8] Guthaus M R, Ringenberg J S, Ernst D, et al. MiBench:a free, commercially representative embedded benchmark suite[C]//Proceedings of the IEEE Workshop on Workload Characterization. New York:IEEE Press, 2001:3-14. [9] Fritts J E, Steiling F W, Tucek J A, et al. MediaBench Ⅱ video:expediting the next generation of video systems research[J]. Microprocessors & Microsystems, 2009, 33(4):301-318. [10] Binkert N, Beckmann B, Black G, et al. The gem5 simulator[J]. Acm Sigarch Computer Architecture News, 2011, 39(2):1-7. [11] Poremba M, Zhang T, Xie Y. NVMain 2.0:a user-friendly memory simulator to model (non-)volatile memory systems[J]. IEEE Computer Architecture Letters, 2015, 14(2):140-143. [12] Ved S, Awasthi M. Exploring non-volatile main memory architectures for handheld devices[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE). New York:IEEE Press, 2018:1528-1531. [13] Samie F, Bauer L, Henkel J. IoT technologies for embedded computing:a survey[C]//International Conference on Hardware/Software Codesign and System Synthesis. New York:IEEE Press, 2016:1-10. [14] Gautschi M, Schiavone P D, Traber A, et al. Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(10):2700-2713. |