北京邮电大学学报

  • EI核心期刊

北京邮电大学学报 ›› 2006, Vol. 29 ›› Issue (4): 99-102.doi: 10.13190/jbupt.200604.99.yangb

• 研究报告 • 上一篇    下一篇

MIMO-OFDM系统定时同步算法的FPGA设计

杨冰,王勇,袁哲明,白洁,张平   

  1. 北京邮电大学 无线新技术研究所,北京 100876
  • 收稿日期:2005-08-24 修回日期:1900-01-01 出版日期:2006-08-30 发布日期:2006-08-30
  • 通讯作者: 杨冰

FPGA Design of Timing Synchronization in MIMO-OFDM System

YANG Bing,WANG Yong,YUAN Zhe-ming,BAI Jie,ZHANG Ping   

  1. Wireless Technology Innovation Institute, Beijing University of Posts and Telecommunications, Beijing 100876, China
  • Received:2005-08-24 Revised:1900-01-01 Online:2006-08-30 Published:2006-08-30
  • Contact: YANG Bing

摘要:

对多入多出-正交频分复用(MIMO-OFDM)系统中基于训练序列的定时同步算法进行了阐述,着眼于系统定时同步算法的硬件实现,对通过FPGA(现场可编程门阵列)实现定时同步算法的复杂度按照单位时间内乘、加次数的方法进行了分析;为降低系统中定时同步算法在FPGA实现过程中的复杂度,对单个定时同步模块内部子模块以及多个定时同步模块间的关系进行了研究,提出了MIMO-OFDM系统定时同步算法的简化实现方案,并对简化方案在Xilinx公司的VirtexII Pro系列FPGA中的资源使用情况进行了统计。研究表明,简化实现方案可以用于MIMO-OFDM系统定时同步算法的硬件实现。

关键词: 定时同步, 多入多出, 正交频分复用, 现场可编程门阵列

Abstract:

Timing synchronization algorithm based on training sequence in multi-input multi-output-orthogonal frequency division multiplexing ( MIMO-OFDM) system were demonstrated. With a view to hardware implementation of timing synchronization algorithm in MIMO-OFDM system, the complexity of timing synchronization algorithm implementation with FPGA(field programmable gate array) was analyzed according to multiplying and adding frequency in unit time. To make the timing synchronization algorithm in MIMO-OFDM system less complicated during FPGA implementation, after study on sub-modules in individual timing synchronizing module and relationship among multiple timing synchronizing modules, a simplified implementation scheme for MIMO-OFDM system timing synchronization algorithm was brought forward, and statistics on resource occupation of such a scheme in VirtexII-Pro series FPGA of Xilinx Company was given. Study shows the simplified implementation scheme is applicable in hardware implementation of MIMO-OFDM system timing synchronization algorithm.

Key words: timing synchronization, multi-input multi-output, orthogonal frequency-division multiplexing, field programmable gate array

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