基于FPGA的高精度时间数字转换电路设计

doi:10.13190/j.jbupt.2019-235

北京邮电大学学报 ›› 2020, Vol. 43 ›› Issue (4): 88-94.doi: 10.13190/j.jbupt.2019-235

基于FPGA的高精度时间数字转换电路设计

戴庆达¹, 叶茂^1,2

1. 天津大学微电子学院, 天津 300072;
2. 天津市成像与感知微电子技术重点实验室, 天津 300072

收稿日期:2019-11-09 发布日期:2020-08-15
作者简介:戴庆达(1994-),男,硕士生,E-mail:daiqingda@126.com;叶茂(1987-),男,副教授.
基金资助:
天津市新一代人工智能科技重大专项项目（18ZXZNGX00230）

Design of Double-Chain Three-Route Time-to-Digital Converter Based on FPGA

DAI Qing-da¹, YE Mao^1,2

1. The School of Microelectronics, Tianjin University, Tianjin 300072, China;
2. Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin 300072, China

Received:2019-11-09 Published:2020-08-15

摘要/Abstract

摘要： 时间数字转换电路（TDC）的分辨率、线性度、温度适应范围等参数指标直接影响着激光雷达系统的测距精度和成像清晰度.基于Xilinx Artix-7系列28 nm工艺的现场可编程门阵列（FPGA）芯片，设计了一种以进位链为延时单元的高分辨率双链三路TDC.该TDC可打破延时单元的分辨率限制，细分进位链中的宽码，具有低成本、高分辨率的优势.设计了流水线编码电路，以提高逻辑单元的使用效率，采用码密度方案逐一确定bin宽的精确值和等效分辨率.调用FPGA中赛灵思的特殊模数转换器（XADC）模块测量芯片温度，进而转换为温度校准系数，修正测量值.常温（27 ℃）下的等效bin宽为5.63 ps，方均根测量数值为11.7 ps，电路可在5~85 ℃温度范围内完成温度补偿.相比于六链延时线TDC，双链三路TDC具有相近的指标参数，并使FPGA逻辑资源使用降低约43.1%，芯片功耗降低约36.8%.

关键词: 现场可编程门阵列, 双链三路时间数字转换电路, 流水线编码器, 码密度方案, 温度补偿

Abstract: The ranging accuracy and image sharpness of radar system are directly related to parameters of time-to-digital converter(TDC), including measurement resolution, linearity, temperature adaptability and so on. A double-chain three-route TDC with high-resolution is designed based on Xilinx 28 nm Artix-7 field programmable gate array(FPGA), which could break the resolution limitation of the single delay tap and effectively subdivide the wide tap. The structure offers significant advantages of low cost and high resolution. The pipeline encoders are designed to economize logic cells. The code density scheme is used to determine the exact value of the bin width one by one and the equivalent resolution. The chip temperature is determined according to the xilinx analog to digital converter module in the FPGA and the temperature calibration coefficient could be obtained to correct the measurement value. Parameter indexes of the TDCs included 5.63 ps equivalent bin width and 11.7 ps root mean square resolution under normal temperature. The compensation is finished in the circuit in the range from 5 ℃ to 85 ℃. Compared with the six-chain delay line TDC, the double-chain three-route TDC has the similar index, which reduces the utilization of logic resources of the FPGA by up to 43.1% and cuts power consumption by up to 36.8% respectively.

Key words: field programmable gate array, double-chain three-route time-to-digital converter, pipeline encoder, code density scheme, temperature compensation

中图分类号:

TN959.74

戴庆达, 叶茂. 基于FPGA的高精度时间数字转换电路设计[J]. 北京邮电大学学报, 2020, 43(4): 88-94.

DAI Qing-da, YE Mao. Design of Double-Chain Three-Route Time-to-Digital Converter Based on FPGA[J]. Journal of Beijing University of Posts and Telecommunications, 2020, 43(4): 88-94.

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基于FPGA的高精度时间数字转换电路设计

Design of Double-Chain Three-Route Time-to-Digital Converter Based on FPGA

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