Open ROADM标准OFEC码在300 Gbit/s FPGA系统中的验证

doi:10.13190/j.jbupt.2020-239

北京邮电大学学报 ›› 2021, Vol. 44 ›› Issue (4): 135-140.doi: 10.13190/j.jbupt.2020-239

• 研究报告 • 上一篇

Open ROADM标准OFEC码在300 Gbit/s FPGA系统中的验证

吴江¹, 许克锋¹, 李允博²

1. 中国移动通信集团有限公司采购共享服务中心, 北京 100045;
2. 中国移动通信集团有限公司研究院, 北京 100045

收稿日期:2020-12-07 发布日期:2021-07-13
作者简介:吴江(1986-),男,工程师,E-mail:wujiangcg@chinamobile.com.

Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System

WU Jiang¹, XU Ke-feng¹, LI Yun-bo²

1. China Mobile Communications Company Limited, Beijing 100045, China;
2. Procurement Shared Service Center, Research Institute of China Mobile Communications Company Limited, Beijing 100045, China

Received:2020-12-07 Published:2021-07-13

摘要/Abstract

摘要： 通过研究开放性可重构光分插复用器（Open ROADM）标准中OFEC码的结构和编译码算法，确定了影响OFEC码算法的性能和实现复杂度的关键参数，并通过业界速率最高的300 Gbit/s现场可编程门阵列（FPGA）验证平台，对不同译码方案在输出误码率为10^-15的性能进行了验证和误码平层分析，对OFEC码在超低误码率下的性能进行了准确评估.

关键词: OFEC码, 现场可编程门阵列, 误码平层, 高速光传输

Abstract: Through studying open forward error correction code (OFEC) code structure and encoding/decoding algorithm in open reconfigu-rable add drop multiplexor(ROADM) standard, the key parameters that influence OFEC performance and implementation complexity are determined. Employing state-of-the-art field programmable gate array emulations platform with a record 300 Gbit/s throughput, the performance of different decoding schemes is evaluated, and the error floor is analyzed at a bit error ratio below 10^-15, which makes the performance evaluation more accurate.

Key words: open forward error correction code, field programmable gate array, error floor, high-speed optical transmission

中图分类号:

TN913

吴江, 许克锋, 李允博. Open ROADM标准OFEC码在300 Gbit/s FPGA系统中的验证[J]. 北京邮电大学学报, 2021, 44(4): 135-140.

WU Jiang, XU Ke-feng, LI Yun-bo. Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System[J]. Journal of Beijing University of Posts and Telecommunications, 2021, 44(4): 135-140.

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Open ROADM标准OFEC码在300 Gbit/s FPGA系统中的验证

Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System

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