北京邮电大学学报

  • EI核心期刊

北京邮电大学学报 ›› 2023, Vol. 46 ›› Issue (3): 19-24.

• 人工智能使能网络通信 • 上一篇    下一篇

一种异构架构的图神经网络加速器优化研究 一种异构架构的图神经网络加速器优化研究

吴进, 赵博, 汶恒, 王宇   

  1. 西安邮电大学 电子工程学院
  • 收稿日期:2022-05-06 修回日期:2022-07-29 出版日期:2023-06-28 发布日期:2023-06-05
  • 通讯作者: 吴进 E-mail:wujin1026@126.com

A Graph Neural Network Accelerator Optimization Research on Heterogeneous Architecture

WU Jin, ZHAO Bo, WEN Heng, WANG Yu   

  • Received:2022-05-06 Revised:2022-07-29 Online:2023-06-28 Published:2023-06-05

摘要:

为了提高图神经网络的算力和效率,对图神经网络训练过程中存在的大量内存需求和随机内存访问等问题进行了研究,提出了一种基于异构架构的高性能图神经网络加速器设计。异构平台采用中央处理器与现场可编程门阵列相结合的方式,主要由计算模块和缓冲模块组成。设计不同的硬件架构进行计算;缓冲模块主要用来有储模型参数和中间变量。针对不规则与规则的聚合和更新2种混合执行方式,改进计算模块,并且对加速器进行数据并行和去除冗余等化。在Ultra96-V2硬件平台上进行实验,结果表明,所设计的图神经网络加速器不仅提升了系统性能,而且显著降低了功率消耗。

关键词: 图神经网络加速器, 异构架构, 混合计算

Abstract:

In order to improve the computational power and efficiency of graph neural networks, the problems of large memory requirements and random memory access in the training process of graph neural networks are studied, and a high-performance graph neural network accelerator design based on heterogeneous architecture is proposed. The heterogeneous platform adopts the combination of central processor and field programmable gate array, which is mainly composed of a calculation module and a buffer module. Design different hardware architectures to implement hybrid computing modules ; the buffer module provides a buffer for the input node features and intermediate variables. Aiming at the two mixed execution modes with irregular and regular aggregation and update, the calculation module is improved, and the accelerator is optimized for data parallelism and redundancy removal. Experiments on the Ultra96-V2 hardware platform show that the designed graph neural network accelerator not only improves the system performance, but also significantly reduces the power consumption.

Key words: graph neural network accelerator, heterogeneous architecture, hybrid computing

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