高速层进式Nand Flash纠错控制编码

北京邮电大学学报 ›› 2010, Vol. 33 ›› Issue (3): 71-74.doi: 10.13190/jbupt.201003.71.hank

韩可,邓中亮,黄建明

HAN Ke, DENG Zhong-liang, HUANG Jian-ming

(School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China)

Received:2009-05-08 Revised:2010-03-11 Online:2010-06-28 Published:2010-05-14

摘要：

由于加工工艺的局限性，在Nand存储器(Nand Flash)控制器设计时应具有处理存储数据出错

的功能，但是还要保持一定的纠错速度. 为解决该问题，在分析常用的差错控制编码(ECC)

算法的基础上，提出了一种高速层进式Nand Flash纠错算法，以提高Nand Flash的读写速度

；同时设计了一个可纠4位错的Nand Flash控制器. 仿真结果表明，采用该编码可有效减少

存储器数据纠错时间. 

关键词: Nand存储器, 差错控制编码, Bose-Chaudhuri-Hocquengham

Abstract:

Because of limitation of the manufacturing technique condition, a Nand Flash

controller is required to handle the bits errors and to maintain the high data

accessing speed. By the analysis of the errorcorrection code (ECC) design meth

od, an acceleratelayerinto error control coding method is proposee to accele

rate the reading and writing process for Nand Flash. A Nand Flash controller

with embedded 4 bit is designed. Simulation shows that the method is effectivel

y reduce the memory data error correction time. 

Key words: Nand Flash, error control coding, Bose-Chaudhuri-Hocquengham

中图分类号:

韩可邓中亮黄建明. 高速层进式Nand Flash纠错控制编码[J]. 北京邮电大学学报, 2010, 33(3): 71-74.

HAN Ke, DENG Zhong-liang, HUANG Jian-ming.

An Accelerate-Layer-Into Error Control Coding Method for Nand Flash [J]. JOURNAL OF BEIJING UNIVERSITY OF POSTS AND TELECOM, 2010, 33(3): 71-74.

PDF