北京邮电大学学报

  • EI核心期刊

北京邮电大学学报 ›› 2016, Vol. 39 ›› Issue (4): 50-55.doi: 10.13190/j.jbupt.2016.04.010

• 论文 • 上一篇    下一篇

基于DDR2 SDRAM的短周期存储方法

唐平, 高飞, 张黎, 蒋志科   

  1. 北京理工大学 信息与电子学院, 北京 100081
  • 收稿日期:2015-12-08 出版日期:2016-08-28 发布日期:2016-08-28
  • 作者简介:唐平(1989-),女,博士生;高飞(1959-),女,教授,博士生导师,E-mail:gaofei@bit.edu.cn.
  • 基金资助:
    二代导航重大专项项目(20100546037)

A Method of Short-Period Storage Based on DDR2 SDRAM

TANG Ping, GAO Fei, ZHANG Li, JIANG Zhi-ke   

  1. School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China
  • Received:2015-12-08 Online:2016-08-28 Published:2016-08-28

摘要: 为了实现某高速实时系统中的大量数据存储需求,提出了一种基于双倍速率同步动态随机存储器的短周期存储方法. 概述了双倍速率同步动态随机存储器控制器的读、写操作基本原理. 为了解决数据持续性交替读入和写出存储器且存取顺序不一致的实际问题,设计了一种短周期存储方法. 按照数据存取方式的不同可分为单次突发和多次突发2种模式,其中少行多列的存储结构可使多次突发模式下短周期读写速度进一步提高. 对基于双倍速率同步动态随机存储器的短周期存储方法进行了性能分析和功能仿真,结果表明,多次突发模式下的短周期存储方法可以少量的现场可编程门阵列片上存储资源和较高的数据读写速率实现存储需求.

关键词: 双倍速率同步动态随机存储器, 短周期存储, 交替存取, 多次突发, 少行多列

Abstract: To meet the storage requirements of mass data in a high-speed and real-time system, a short-period storage method based on double data rate 2 synchronous dynamic random access memory(DDR2 SDRAM) was proposed. First, the basic principles of reading and writing operation of DDR2 SDRAM controller are summarized. Then, in order to solve the practical problem of reading and writing data in different orders continuously and alternately, a short-period storage method was designed, which can be divided into two modes of single burst and multiple burst according to the different data access modes. In the multiple burst mode of short-period storage method, the storage structure of fewer rows and more columns can further improve the speed of reading and writing data. At last, the performance analysis and function simulation of the short-period storage method based on DDR2 SDRAM is carried out. It is shown that the short-period storage method in the mode of multiple burst can achieve the storage requirement with a small amount of internal storage resource of field-programmable gate array(FPGA) and high speed of reading and writing data.

Key words: double data rate 2 synchronous dynamic random access memory, short-period storage, alternate access, multiple burst, fewer rows and more columns

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