| [1] Daemen J, Rijmen V. AES proposal: Rijndael[C]//First Advanced Encryption Standard (AES) Conference. US: NIST, 1998.[2] WG802.15.802.15.4—2006, IEEE standard for information technology—local and metropolitan area networks—specific requirements—Part 15.4: wireless medium access control (MAC) and physical layer (PHY) specifications for low rate wireless personal area networks (WPANs) [S]. IEEE, 2007.[3] ISA-100. 11a—2009, Wireless systems for industrial automation: process control and related applications[S]. ISA , 2009.[4] Rahimunnisa K, Karthigaikumar P, Kirubavathy J, et al. A 0.13-μm implementation of 5Gb/s and 3-mW folded parallel architecture for AES algorithm[J]. International Journal of Electronics, 2013 (ahead-of-print): 1-12.[5] Wang Yi, Ha Yajun. A performance and area efficient ASIP for higher-order DPA-resistant AES[J]. Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, 2014, 4(2): 190-202.[6] Jeffrey. Intel® advanced encryption standard instructions (AES-NI) [EB/OL]. 2012[2013] . https: //software. intel. com/en-us/ articles/intel-advanced-encryption-standard-instructions-aes-ni.[7] Yumbul K, Sava E, Kocaba Ö, et al. Design and implementation of a versatile cryptographic unit for risc processors[J]. Security and Communication Networks, 2014, 7(1): 36-52.[8] Liu Bin, Baas B M. Parallel AES encryption engines for many-core processor arrays[J]. Computers, IEEE Transactions on, 2013, 62(3): 536-547.[9] Schneider, T, Von Maurich, I, Guneysu, T. Efficient implementation of cryptographic primitives on the GA144 multi-core architecture[C]//Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on. US: IEEE, 2013: 67-74.[10] Rebeiro C, Selvakumar D, Devi A S L. Bitslice implementation of AES[C]//5th International Conference, CANS 2006. Germany: Springer Berlin Heidelberg, 2006: 203-212.[11] Gladman B. A specification for Rijndael, the AES algorithm[EB/OL]. 2001[2013] . http://fp. gladman. plus. com/cryptography_technology/rijndael/aes. spec. 311. pdf.[12] Bertoni G, Breveglieri L, Fragneto P, et al. Efficient software implementation of AES on 32-bit platforms[C]//Cryptographic Hardware and Embedded Systems-CHES 2002. Germany: Springer Berlin Heidelberg, 2003: 159-171.[13] Atasu K, Breveglieri L, Macchetti M. Efficient AES implementations for ARM based platforms[C]//Proceedings of the 2004 ACM Symposium on Applied Computing. US: ACM, 2004: 841-845.[14] Babu M R, Reddy A R. Optimization of memory for AES Rijndeal algorithm implementation on embedded system[J]. IJCSNS, 2013, 13(9): 105.[15] Bellare M, Kilian J, Rogaway P. The security of cipher block chaining[C]//Advances in Cryptology—CRYPTO'94. Germany: Springer Berlin Heidelberg, 1994: 341-358.[16] Lipmaa H, Wagner D, Rogaway P. Comments to NIST concerning AES modes of operation: CTR-mode encryption[C]//Symmetric Key Block Cipher Modes of Operation Workshop. US: National Institute of Science and Technology, 2000. |
