Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System

doi:10.13190/j.jbupt.2020-239

Journal of Beijing University of Posts and Telecommunications ›› 2021, Vol. 44 ›› Issue (4): 135-140.doi: 10.13190/j.jbupt.2020-239

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Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System

WU Jiang¹, XU Ke-feng¹, LI Yun-bo²

1. China Mobile Communications Company Limited, Beijing 100045, China;
2. Procurement Shared Service Center, Research Institute of China Mobile Communications Company Limited, Beijing 100045, China

Received:2020-12-07 Published:2021-07-13

Abstract

Abstract: Through studying open forward error correction code (OFEC) code structure and encoding/decoding algorithm in open reconfigu-rable add drop multiplexor(ROADM) standard, the key parameters that influence OFEC performance and implementation complexity are determined. Employing state-of-the-art field programmable gate array emulations platform with a record 300 Gbit/s throughput, the performance of different decoding schemes is evaluated, and the error floor is analyzed at a bit error ratio below 10^-15, which makes the performance evaluation more accurate.

Key words: open forward error correction code, field programmable gate array, error floor, high-speed optical transmission

CLC Number:

TN913

WU Jiang, XU Ke-feng, LI Yun-bo. Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System[J]. Journal of Beijing University of Posts and Telecommunications, 2021, 44(4): 135-140.

References

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Verification of OFEC Code under Open ROADM Standard in 300 Gbit/s FPGA System

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