Abstract: The asymmetric partitioning mode introduced in the high efficiency video coding (HEVC) standard results in a double increase of the sum of absolute difference (SAD) operation amount in the motion estimation algorithm. In order to improve the efficiency of motion estimation algorithm, it is convenient for users to choose independently, a reconfigurable array structure is designed which supports both the opening and closing of an asymmetric partitioning mode and the free switching between execution modes. In order to satisfy the user's requirement for coding speed, and maximize the use of the resources of the reconfigurable array processor, 16×8, 16×4, and 16×2 processing elements are loaded in an array structure of 16×16 processing elements. The instruction is used to dynamically reconfigure the array size, and different instructions are sent to corresponding processing elements for corresponding configuration by means of the instruction issuance manner. The experimental results show that the proposed reconfigurable implementation approach reduces the processing time by about 35% and the throughput is improved by about 0.4 times compared with the streamlining under the condition that the hardware resource occupancy closely. The implementation has high execution efficiency, and can switch between execution mode and array size, and has better flexibility.

Key words: high efficiency video coding, sum of absolute difference, reconfigurable, asymmetric method partition