Journal of Beijing University of Posts and Telecommunications

  • EI核心期刊

JOURNAL OF BEIJING UNIVERSITY OF POSTS AND TELECOM ›› 2014, Vol. 37 ›› Issue (1): 85-89.doi: 10.13190/j.jbupt.2014.01.019

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Design of Satellite Borne FPGA Basedon (16,8) Quasi-Cyclic Code for Fault-Tolerant Finite State Machines

FENG Shui-chun, MENG Xin, MAO Bo-nian, BIAN Chun-jiang   

  1. National Space Science Center, Chinese Academy of Science, Beijing 100191, China
  • Received:2013-01-15 Online:2014-02-28 Published:2014-01-07

Abstract:

The stabilities of finite-state machine (FSM) seriously affects the normal operation of satellite borne system, and is important for control logic. Single event upset caused by space radiation environment often leads to FSM instabilities. Current fault-tolerant methods can correct single error. However, the correction of double errors for those high reliability systems is also necessary. A new design of field program gate array(FPGA) based on (16,8) quasi-cyclic code was presented. With advantages of high reliability, uncomplicated hardware and short delay. The design can correct single or double errors, and detect triple errors as well.

Key words: stabilities of finite-state machine, single event upset, field program gate array, finite-state machine, fault-tolerant, quasi-cyclic code

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