面向阵列处理器的分布式共享存储结构设计

doi:10.13190/j.jbupt.2017.04.002

北京邮电大学学报 ›› 2017, Vol. 40 ›› Issue (4): 9-15.doi: 10.13190/j.jbupt.2017.04.002

面向阵列处理器的分布式共享存储结构设计

山蕊¹, 沈绪榜¹, 蒋林², 朱筠², 宋辉²

1. 西安电子科技大学微电子学院, 西安 710071;
2. 西安邮电大学电子工程学院, 西安 710121

收稿日期:2016-10-18 出版日期:2017-08-28 发布日期:2017-07-10
作者简介:山蕊(1986-),女,博士生,E-mail:shanrui0112@163.com;沈绪榜(1933-),男,院士,博士生导师.
基金资助:
国家自然科学基金项目（61272120，61634004，61602377）；陕西省科技统筹计划项目（2016KTZDGY02-04-02）；陕西省教育厅专项科研计划项目（17JK0689）

Design of Distributed Shared Memory Structure for Array Processor

SHAN Rui¹, SHEN Xu-bang¹, JIANG Lin², ZHU Yun², SONG Hui²

1. School of Microelectronics, Xidian University, Xi'an 710071, China;
2. School of Electronic Engineering, Xi'an University of Posts and Telecommunication, Xi'an 710121, China

Received:2016-10-18 Online:2017-08-28 Published:2017-07-10

摘要/Abstract

摘要： 为了缓解随处理器核数增多而被激化的"存储墙"问题，提出了局部高速交叉互连、全局片上网络互连的两级混合互连网络结构，设计了支持统一编址方式的数据传送机制.在现场可编程门阵列上实现了2种规模的存储结构，对面积、时序和功耗进行统计.基于SystemC开发了混合仿真平台，仿真结果表明，所提结构具有较高的存储访问带宽和较低的局部数据访问延迟.

关键词: 阵列处理器, 存储结构, 片上网络, 分布式存储, 统一编址

Abstract: With the increasing of number of processors, the problem of memory wall was more severely. In order to alleviate this problem, two-level mixed interconnection network was proposed: fast crossbar for local data transfer and network on chip for long distance data communication. Meanwhile data transfer mechanism was designed to support unified addressing. Two memory architecture sizes were implemented on field rpogrammable gate array, and area, frequency and power consumption were evaluated. A mixed simulation testbench based on SystemC language was developed. The simulation results show that the designed architecture has higher memory access bandwidth and lower local accessing latency.

Key words: array processor, memory structure, network on chip, distributed memory, unified addressing

中图分类号:

TN492

山蕊, 沈绪榜, 蒋林, 朱筠, 宋辉. 面向阵列处理器的分布式共享存储结构设计[J]. 北京邮电大学学报, 2017, 40(4): 9-15.

SHAN Rui, SHEN Xu-bang, JIANG Lin, ZHU Yun, SONG Hui. Design of Distributed Shared Memory Structure for Array Processor[J]. JOURNAL OF BEIJING UNIVERSITY OF POSTS AND TELECOM, 2017, 40(4): 9-15.

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面向阵列处理器的分布式共享存储结构设计

Design of Distributed Shared Memory Structure for Array Processor

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