关键词: 片上系统, 测试调度, 测试环, 测试访问机制, 序列对

Abstract:

A deterministic algorithm is proposed for System-on-Chip (SOC) test scheduling. With the optimal assignment and balance design for test wrappers, four types of incremental Sequence Pair generation methods are constructed as a cyclic iteration process. By considering the TAM width, dead space, and test area for IP cores simultaneously, the algorithm can achieve effective solutions in certain iteration steps. Experimental results on ITC’02 benchmark show that the proposed algorithm performs faster than the traditional SA method while obtaining comparable results.

Key words: system-on-chip, test scheduling, test wrapper, test access mechanism, sequence pair