Abstract: The ranging accuracy and image sharpness of radar system are directly related to parameters of time-to-digital converter(TDC), including measurement resolution, linearity, temperature adaptability and so on. A double-chain three-route TDC with high-resolution is designed based on Xilinx 28 nm Artix-7 field programmable gate array(FPGA), which could break the resolution limitation of the single delay tap and effectively subdivide the wide tap. The structure offers significant advantages of low cost and high resolution. The pipeline encoders are designed to economize logic cells. The code density scheme is used to determine the exact value of the bin width one by one and the equivalent resolution. The chip temperature is determined according to the xilinx analog to digital converter module in the FPGA and the temperature calibration coefficient could be obtained to correct the measurement value. Parameter indexes of the TDCs included 5.63 ps equivalent bin width and 11.7 ps root mean square resolution under normal temperature. The compensation is finished in the circuit in the range from 5 ℃ to 85 ℃. Compared with the six-chain delay line TDC, the double-chain three-route TDC has the similar index, which reduces the utilization of logic resources of the FPGA by up to 43.1% and cuts power consumption by up to 36.8% respectively.

Key words: field programmable gate array, double-chain three-route time-to-digital converter, pipeline encoder, code density scheme, temperature compensation