Power Integrity Analysis of FPGA Heterogeneous Accelerate Board

doi:10.13190/j.jbupt.2017-238

JOURNAL OF BEIJING UNIVERSITY OF POSTS AND TELECOM ›› 2018, Vol. 41 ›› Issue (4): 76-80.doi: 10.13190/j.jbupt.2017-238

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Power Integrity Analysis of FPGA Heterogeneous Accelerate Board

YANG Zheng^1,2, KAN Hong-wei¹, LIU Tie-jun¹, ZHANG Chuang¹

1. Architecture Research Department, Inspur Group Company Limited, Jinan 250000, China;
2. State Key Laboratory of High-End Server and Storage Technology, Inspur Group Company Limited, Beijing 100085, China

Received:2017-12-23 Online:2018-08-28 Published:2018-10-09

Abstract

Abstract: A high performance and high density field programmable gate array (FPGA) heterogeneous accelerate board was proposed. Base on target impedance design method, the AC/DC characteristics were analyzed and power integrity post simulation was present. Application on image identification utilized the proposed heterogeneous FPGA accelerate board and performance comparison are given.

Key words: power integrity, power distribution network, target impedance, decoupling capacitor

CLC Number:

TN402

YANG Zheng, KAN Hong-wei, LIU Tie-jun, ZHANG Chuang. Power Integrity Analysis of FPGA Heterogeneous Accelerate Board[J]. JOURNAL OF BEIJING UNIVERSITY OF POSTS AND TELECOM, 2018, 41(4): 76-80.

References

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Power Integrity Analysis of FPGA Heterogeneous Accelerate Board

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