| [1] Zhan Guo, Nilsson P. VLSI architecture of the square root algorithm for V-BLAST detection [J]. VLSI Signal Process, 2006, 44(3): 219-230.[2] Troya A, Maharatna K, Krstic M, et al. Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems [J]. IEEE Trans. Circuits Syst. I, Reg. Papers, 2008, 55(2): 672-686. [3] Khan Z, Arslan Z, et al. Analysis and implementation of multiple-input, multiple-output VBLAST receiver from area and power efficiency perspective[J]. IEEE Trans. Very Large Scale Integration, 2006, 14(11): 1281-1286. [4] Sobhanmanesh F, Nooshabadi S. Parametric minimum hardware QR-factoriser architecture for V-BLAST detection [J]. Proc. IEE Circuits, Devices and Sys, 2006, 153(5): 433-441. [5] Lang T, Antelo E. High-throughput CORDIC-based geometry operations for 3D computer graphics [J]. IEEE Trans. Computers, 2005, 54(3): 347-361. [6] Molina A, Cadence O. Function verification: approaches and challenges [J]. Latin American Applied Research, 2007, 37(1): 65-69. [7] Guzey O, Li Chungwang. Coverage-directed test generation through automatic constraint extraction [C]//The IEEE International High Level Design Validation and Test Workshop. Washington: IEEE Computer Society, 2007: 151-158. [8] Modi D, Sitapara H, et al. Integrating MATLAB with verification HDLs for functional verification of image and video processing ASIC[J]. International Journal of Computer Science & Emerging Technologies, 2011, 2(2): 258-265. [9] Kwang Y L, Tae R P, et al. A virtual simulation environment for a design & verification of a GPGPU[J]. World Academy of Science, Engineering and Technology, 2011, 54(1): 417-421. [10] Popovic I, Vrtunski V, et al. Formal verification of distributed transaction management in a SOA based control system[C]//18th IEEE International Conference and Workshops on Engineering of Computer-Based System. USA: IEEE Computer Society, 2011: 206-215. |
