Abstract: Proposes a VLSI architecture of EBCOT, in which a Dynamic Memory Control ( DMC) is adopted to reduce 60% scale of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be used as a compact and efficient IP core for JPEG2000 V LSI implementation and various realtime image /video applications.

Key words: EBCO T, DMC, JPEG2000