Abstract:

A reconfigurable processor is presented to execute the loop automatically in reconfigurable cell array. Data distribution and asymmetric first in first out buffer (FIFO) can speedup the data transfer with 8 times. The hardware architecture is verified on the platform of fieldprogrammable gate array (FPGA) with some kernel algorithms of multimedia applications such as integer invert discrete cosine transform (IDCT) and motion estimation of advanced video coding of moving pictures experts group4 (H.264) and IDCT of moving pictures experts group2(MPEG2). With a same scale of reconfigurable array, the performance will be 35 times higher than the similar researches.

Key words: reconfigurable processor, reconfigurable array, loop mapping